In high-speed serial communication, it is well-known that an eye pattern is closed at a data receiving end of a receiver due to inter-symbol interference, referred to below as ISI, due to, for example, the frequency dependency of the loss on a transmission line, thus deteriorating a bit error rate.
There has been known a waveform equalization technique, termed decision feedback equalization (DFE), which compensates waveform deterioration due to ISI on the receiving circuit side.
The DFE is a waveform equalization technique that negatively feeds back an amount of succeeding ISI(Inter-Symbol Interference), corresponding to the result of decision of a received signal by a data decision circuit, to succeeding bits to remove ISI. As regards the DFE, reference is had to, for example, the disclosure of the Non-Patent Document 1.
In the present patent application, the DFE in which the period of the feedback signal is the data rate period (T) is termed the ‘full-rate DFE’, and the DFE in which the period of the feedback signal is twice the data rate period (2T) is referred to as ‘half-rate DFE’.
In high-speed serial communication, such a scheme in which full-rate data is transmitted/received using a rise edge timing of a differential clock having a period (2T) equal to twice the data rate period (T), known as ‘half-rate clock’, is mainly adopted. This system is known as ‘double-data rate system’.
In the double-data rate system, the data rate communication of 10 Gb/s, for example, is implemented using a differential clock of 5 GHz.
As an example, description is now made of the 1-tap DFE equalization operation of the double-data rate system with reference to FIGS. 1 and 2.
To a received signal 110 are added an odd DFE decision feedback signal 116 and an even DFE decision feedback signal 126, respectively, in an odd DFE adder 111 and an even DFE adder 121, which output DFE-equalized added signals 112 and 122, respectively.
These DFE-equalized added signals 122 and 122 are interleave-sampled by an odd data sampling unit 113 and an even data sampling unit 123, respectively, at a timing of an odd half-rate clock 118 and at a timing of an even half-rate clock 128, respectively.
Odd sampling data 114 from the odd data sampling unit 113 and even sampling data 124 from the even data sampling unit 123 are multiplied by tap gains 117 and 127, respectively.
An output of the tap gain 127, which is the odd DFE decision feedback signal 116, is negatively fed back to the odd DFE adder 111 as a signal to be added. An output of the tap gain 117, which is the even DFE decision feedback signal 126, is negatively fed back to the even DFE adder 121 as a signal to be added.
This DFE equalization by negative feedback removes ISI to enable correct data reception.
The DFE operation of the 1-tap double-data rate configuration will now be described using data d1, d2 and d3 of FIG. 2.
In the following, the data rate period is assumed to be T, with the half-rate clock period being 2T (in 10 Gbps communication, the data rate period T=100 ps and the half rate clock period 2T=200 ps).
To the received data d2 influenced by ISI, is added a decision feedback signal, corresponding to an odd sampling data d1 multiplied by a tap gain (α), to generate a DFE-equalized even added signal:d2+α×d1
This DFE-equalized waveform is correctly sampled at an even half-rate clock to yield an even sampling data d2 with a period of 2T.
This DFE equalized waveform is correctly sampled at an even half-rate clock to generate even sampling data d2 with the period of 2T.
To remove ISI on an odd sampling data d3 by the sampling data d2, the odd DFE decision feedback signal 116 (=α×d2), corresponding to d2 multiplied by the tap gain (α), is fed back to the odd DFE adder 111. The odd DFE decision feedback signal 116 is added in this odd DFE adder 111 to the received signal d3 so that the signal d3 is DFE-equalized.
This negative feedback process is repeated to realize DFE equalization of the double data rate system.
It should be noted that, since the double-data rate system samples data at a half-rate clock, the sampling data is of the period 2T equal to twice the data rate period T.
As a result, one of two signals to be added in the DFE adder is a received signal of the sampling data period of 2T, while the other is a received signal of the data rate period T.
The data waveform-equalized by DFE of FIG. 1 is only data at an odd or even sampling timing. Hence, the signals output from the DFE adders may be waveform equalized only at a rate of one per two data at each of the even and odd sides. As a result, there is produced a waveform which is an alternate repetition of waveform-equalized open eye data and non-waveform-equalized closed eye data, as shown in FIG. 4.
[Non-Patent Document 1]
Meghelli, Mounir; Rylov, Sergey; Bulzacchelli, John; Rhee, Woogeun, Rylyakov, Alexander; Ainspan, Herscel; Parker, Benjamin; Beakes, Michael; Chung, Aichin; Beukema, Troy; Pepeljugoski, Petar; Shan, Lei; Kwark, Young; Gowda, Sudhir; Friedman, Daniel, “A 10 Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology”, IEEE International Solid-State Circuits Conference, February 2006